This invention relates to the processing of digital signals. It is of particular utility in a system in which digital signals are broadcast or otherwise transmitted from one location to another.
When a stream of digital data is received for processing, it is necessary to establish a clock rate in the processor that is synchronized with the clock rate or received data. Some systems of digital encoding have one or more level transitions in each digit so that each digit carries its own synchronizing information. Such systems are seldom of use where digital signals are broadcast over radio channels since the price of carrying clock information in each bit is the requirement of additional bandwidth. For radio communication within channels of fixed bandwidth this would represent a required reduction in the data rate. A system for clock recovery from digital data that does not include a transition in each bit must provide a clock that is free-running when no synchronizing transitions occur. The clock must be able to maintain adequate synchronization with the received bit stream despite the presence of runs of time in which there may be no transitions of level to establish the edge of a digit. The system must be sufficiently tolerant of noise that it does not readily lose synchronism with the digital signal in the presence of random noise pulses. With the usable range of a radio communication system determined by the ability to distinguish signals from noise, it is important to minimize the loss of intelligibility stemming from poor synchronism, thus shifting the cause to the corruption of an individual digit by noise.
One final requirement for a clock recovery system is a compromise between two apparently inconsistent requirements. When one first attempts to establish communication with an incoming signal, it is desirable to establish synchronism as fast as possible. A clock recovery system that is initially out of synchronism should change rapidly to establish synchronism. However, if it changes fast to become synchronized, it may also change equally as fast to become unsynchronized in the presence of random noise pulses. This is undesirable.
Various methods have been used in the past to achieve synchronism or controlled timing in recovery circuits. Such systems normally involve phase-locked loops of one kind or another. One approach is to adjust the phase of recovered clock pulses by a variable amount. The variable amount is determined by taking the difference between the recovered clock pulses and the input signal and applying that phase difference to adjust the phase of the recovered clock pulse. Such a system is characterized, like most error-sensitive systems, by a phase adjustment that varies in size according to the amount of error. Such a system has poor tolerance to noise because it can easily become unsynchronized. Another approach that has been taken is to use an up-down counter to indicate whether the input data signal is synchronized with the recovered clock. If one is ahead of the other, that fact is indicated on the up-down counter which causes corrections that are proportional to the difference in phase. Common to each of the systems described is a sensitivity level that is fixed regardless of the difference between the clock rate of the input data and the recovered clock signal.
It is an object of the present invention to provide a better circuit for recovering clock signals in a digital data stream.
It is a further object of the present invention to provide a method of clock recovery that allows fast correction of large changes in phase between an input bit stream and recovered clock pulses.
It is a further object of the present invention to provide a circuit that is sensitive in responding to a need for small changes in clock phase to maintain synchronism.
Other objects will become apparent in the course of a detailed description of the invention.